Priority is claimed from European Application No. 02 013 141 filed Jun. 14, 2002 under 35 U.S.C. xc2xa7 119.
The invention relates to an electronic circuit for a switching power amplifier, to a switching power amplifier, to an integrated circuit comprising an electronic circuit for a switching power amplifier and to a device comprising a switching power amplifier. The invention relates equally to a method for switching the output stage of a switching power amplifier.
It is well known to employ switching power amplifiers in a variety of fields, e.g. in motor control, as switching RF (radio frequency) power amplifiers or as class D audio amplifiers, wherein amplifiers are categorized into class A, B, C, D, etc. by their properties. Typically, the load of a switching amplifier is a circuit containing an inductive component, for instance a motor or a speaker.
The main motivation to use switching power amplifiers is their high power efficiency. In portable devices, like mobile phones, a high power efficiency increases the operation time and decreases the heat dissipation and the resulting heating of the device. Another reason for using switching power amplifiers instead of linear amplifiers is the difficulties in implementing linear amplifiers with current low-voltage semiconductor technologies.
In switching power amplifiers, the output power provided to a load is controlled by switching power switches in the output stage of the amplifier. The output stage of a switching power amplifier can be implemented instance with PMOS and NMOS transistors or with PNP and NPN transistors in an inverter topology, where the transistors constitute controllable power switches of the output stage. The output stage can further be single-ended or differential.
FIG. 1 illustrates the principle of a single-ended output stage of a switching power amplifier. In FIG. 1, a PMOS transistor Vp and an NMOS transistor Vn, connected in series between a voltage supply 11 and ground 12, constitute a single-ended output stage. The transistors Vp, Vn are controlled by a common input signal Vpwl. The input signal Vpwl has an alternating polarity and is provided by clocking means not shown in the figure. The output of the output stage is provided between the two transistors Vp, Vn. Currently, a load 13 is connected to this output. At the output of the output stage, a voltage Vout is provided to the connected load 13. Due to the alternating input signal Vpwl, the output stage alternates between a first phase, in which a current is able to flow from load 13 via transistor Vn to ground 12, and a second phase, in which a current is able to flow from voltage supply 11 via transistor Vp to load 13. In a situation in which both transistors Vp, Vn are turned on, a current Ithrough may flow from the branch comprising transistor Vp to the branch comprising transistor Vn. Alternatively, a separate input signal could be provided to the two transistors Vp, Vn.
A differential output stage, which is also referred to as H bridge, can be implemented by combining two appropriately clocked single-ended output stages. The load is arranged in this case between the outputs of the two single-ended switching stages. FIG. 2 illustrates the principle of such a differential output stage.
On the one hand, a first PMOS transistor Vp1, and a first NMOS transistor Vn1 are connected in series between a voltage supply 21 and ground 22. On the other hand, a second PMOS transistor Vp2 and a second NMOS transistor Vn2 are connected in series between voltage supply 21 and ground 22. The connection between transistors Vp1, and Vn1 forms a first output of the differential output stage, and the connection between transistors Vp2 and Vn2 forms a second output of the differential output stage. Currently, a load 23 is connected between the first and the second output of the output stage. The output voltage at the first output is referred to as Vout1, while the output voltage at the second output is referred to as Vout2.
The four transistors are controlled such that the signals input on the one hand to transistors Vn1, and Vp1, and on the other hand to transistors V2 and Vp2 have mainly an opposite, alternating polarity. This can be achieved in different ways. In one alternative, each of the transistors is controlled with a separate input signal. In another alternative, transistors Vp1 and Vn1 are controlled with a first input signal Vpwl1, while transistors Vp2 and Vn2 are controlled with a second input signal Vpwl2. The input signals Vpwl1 and Vpwl2 can be provided e.g. by a class BD modulation block. Class BD is used for three-level class D switching amplifiers. This second possibility is indicated in FIG. 2 with a dashed line between a first input signal Vpwl1 fed to transistor Vn1 and transistor Vp1, and with a dashed line between a second input signal Vpwl2 fed to transistor Vn2 and transistor Vp2 In a further alternative, all transistors are controlled by a single input signal. To this end, an input signal Vpwl1 is provided by clocking means (not shown) and fed to transistors Vn1 and Vp1 as in the second alternative, while the input signal for transistors Vn2 and Vp2 is obtained by an inverter 24, to which input signal Vpwl1 is fed. Thereby, a separate second input signal Vpwl2 is not required. This possibility is indicated in FIG. 2 with additional dotted lines.
Due to the alternating input signals, e.g. Vpwl1 and Vpwl2, the output stage alternates between a first phase a, in which a current is able to flow from voltage supply 21 via transistor Vp2, load 23 and transistor Vn1 to ground 22, and a second phase b, in which a current is able to flow from voltage supply 21 via transistor Vp1, load 23 and transistor Vn2 to ground 22.
In both cases, i.e. in the case of a single-ended output stage and in the case of differential output stages, the transition between the respective first phase and the respective second phase can be realized by switching the power switches of the output stage in an overlapping mode or in a non-overlapping mode.
FIG. 3A illustrates a non-overlapping switching and FIG. 3B an overlapping switching for the differential output stage presented in FIG. 2. In both figures, the signals provided to the transistors Vn1, Vp2, Vn2 and Vp1 are shown for two consecutive transitions, more specifically for a first transition from phase a to phase b and for a subsequent transition back to phase a. For both transitions, a reference time is indicated by a vertical dotted line.
A non-overlapping mode can be achieved for a differential switching stage as depicted in FIG. 2 by providing four separate switching signals for transistors Vp1, Vn1, Vp2 and Vn2. In FIG. 3A, the non-overlapping signals supplied to transistors Vn1 and transistor Vp1 have a high level in the initial phase a, while the signals supplied to transistor Vp2 and transistor Vn2 have a low level in the initial phase a. Shortly before the reference time for the first transition from phase a to phase b, the signal supplied to transistor Vn1 is switched to a low level and the signal supplied to transistor Vp2 is switched to a high level. This has the effect of turning the transistors Vn1 and Vp2 off such that all power transistors are turned off. Shortly after the reference time for the first transition, the signal supplied to transistor Vn2 is switched to a high level and the signal supplied to transistor Vp1 is switched to a low level. This has the effect of turning the transistors Vn2 and Vp1 on. Shortly before the reference time for the second transition back from phase b to phase a, the signal supplied to transistor Vn2 is switched again to a low level and the signal supplied to transistor Vp1 is switched again to a high level. This has the effect of turning the transistors Vn2 and Vp1 off such that all power transistors are turned off again. Shortly after the reference time for the second transition, the signal supplied to transistor Vn1 is switched again to a high level and the signal supplied to transistor Vp2 is switched again to a low level. This has the effect of turning the transistors Vn1 and Vp2 on. For both transitions, thus all of the transistors Vn1, Vp2, Vn2 and Vp1 are briefly turned off at the same time during the period of time between the switching shortly before the respective reference time and the switching shortly after the respective reference time.
A non-overlapping mode can be achieved correspondingly for a single ended switching stage as depicted in FIG. 1 by providing two separate switching signals for transistors Vp and Vn.
An overlapping mode can be achieved for a differential switching stage as depicted in FIG. 2 with a single common input signal, with two input signals or with four separate switching signals for transistors Vp1, Vn1, Vp2 and Vn2 as described above with reference to FIG. 2. In FIG. 3B, the overlapping signals supplied to transistor Vn1 and transistor Vp1 have as well a high level in the initial phase a, while the signals supplied to transistor Vp2 and transistor Vn2 have as well a low level in the initial phase a. In this case, however, the signal supplied to transistor Vn2 is switched to a high level and the signal supplied to transistor Vp1 is switched to a low level already shortly before the reference time for the first transition from phase a to phase b. The signal supplied to transistor Vn1 is switched to a low level and the signal supplied to transistor Vp2 is switched to a high level only shortly after the reference time for the first transition. Accordingly, shortly before the reference time for the second transition back from phase b to phase a, the signal supplied to transistor Vn1 is switched again to a high level and the signal supplied to transistor Vp2 is switched again to a low level. Shortly after the reference time for the second transition, the signal supplied to transistor Vn2 is switched again to a low level and the signal supplied to transistor Vp1 is switched again to a high level. For both transitions, thus all of the transistors V1, Vp2, Vn2 and Vp1 are briefly turned on at the same time during the period of time between the switching shortly before the respective reference time and the switching shortly after the respective reference time.
An overlapping mode can be achieved correspondingly for a single ended switching stage as depicted in FIG. 1 by providing a single switching signal or two separate switching signals for transistors Vp and Vn.
The clocking sequence employed for switching the output stage depends on the pulse width modulation (PWM) scheme used. A typical PWM scheme is class BD.
Regardless of the modulation used, some problems may occur during the switching of the power switches as well in the case of single-ended output stages as in the case of differential output stages.
A first type of problem occurs if the effective clocking is overlapping, as illustrated in FIG. 3B. Even in case all power switches conduct simultaneously only for a short period of time, large current spikes will flow from the voltage supply through the power switches to ground.
FIG. 4 illustrates a current spike occurring when an overlapping switching is employed for the single-ended switching power output stage of FIG. 1. FIG. 4 shows the course of the input signal Vpwl and of the current Ithrough over time. The input signal Vpwl is changing gradually from a low level to a high level for switching the output stage in overlapped mode. Both transistors Vp and Vn will conduct at the same time over a certain voltage range of Vpwl during this gradual change. This implies that there is a voltage range in which a large current Ithrough will flow through both transistors Vp and Vn during the rising and falling edges of the input signal Vpwl.
Such current spikes reduce the efficiency of the power amplifier. Further, they cause EMC (electromagnetic compatibility) noise and ripples to the supply voltage line which can disturb the operation of other blocks using the same voltage supply.
A second type of problem occurs if the effective clocking is non-overlapping, as shown in FIG. 3A. Even in case all power switches are turned off simultaneously only for a short period of time, a large voltage over-shoot will occur due to the inductive nature of the load, which tries to keep the current through it flowing. The latter effect is also referred to as xe2x80x9ccurrent kickbackxe2x80x9d. The over-shoot voltage magnitude is usually limited to a typical value of one diode drop, i.e. to 0.7 V, by the ESD (electrostatic discharge) circuitry in the IO (input/output) cells. While all power switches are turned off, the current in the load inductance is therefore pushed through the ESD circuitry to the substrate of the chip generating substrate noise. The voltage over-shoot is thus a source of noise for the other circuitry in the same chip.
There is also a potential reliability risk when stressing the ESD circuitry with repeated current spikes occurring during overlapped switching transitions or a repeated voltage overshoot occurring with non-overlapped switching transitions. The ESD structures can be dimensioned large enough to avoid a degradation of the reliability, but this leads to an increase in semiconductor area which is not required for the regular functions of the power amplifier.
It is also known to avoid the described problems with additional or separate protection devices, like diodes etc. Additional components, however, result as well in an increase of the required space.
Another well-known source of EMC noise in switched power amplifiers is the abrupt edges of the output pulse stream. The spectrum of the output signal contains a significant power at the switching frequency and its harmonics, typically to tens of MHz
It is an object of the invention to reduce the problems occurring during the switching of the output stage of a switching power amplifier.
This object is reached according to the invention with an electronic circuit for a switching power amplifier, which electrical circuit comprises at least two switching stages forming an output stage. Each of the switching stages comprises at least two controllable power switches and provides an output between the at least two controllable power switches. The at least two switching stages are moreover connected with regard to their outputs in parallel to each other. The proposed electronic device comprises in addition clocking means for switching the controllable power switches of the at least two switching stages. The clocking means switch the controllable power switches of at least one of the switching stages in an overlapped mode and the controllable power switches of at least one other of the switching stages in a non-overlapped mode.
The object of the invention is equally reached with a switching power amplifier comprising the proposed electronic circuit, with an integrated circuit comprising the proposed electronic circuit and with a device comprising a switching power amplifier with the proposed electronic circuit.
Finally, the object of the invention is reached with a method for switching an output stage of a switching power amplifier, which output stage includes at least two switching stages, wherein each of the switching stages includes at least two controllable power switches and provides an output between said at least two controllable power switches, and wherein the at least two switching stages are connected with regard to their outputs in parallel to each other. It is proposed that the method comprising switching the controllable power switches of at least one of the switching stages in an overlapped mode and switching the controllable power switches of at least one other of the switching stages in a non-overlapped mode.
The invention proceeds from the idea that the problems occurring during the switching of the output stage can be avoided, if the output stage is composed of several switching stages in parallel, some of which are clocked in an non-overlapped fashion and some of which are clocked in an overlapped fashion.
Compared to an exclusively overlapped switching of the output stage, it is an advantage of the invention that it reduces the large current rush through the power switches occurring during the transitions to an acceptable level. The reduction of current spikes taken from the power supply leads to a reduction of EMC noise and as well to a reduction ripples caused to the supply voltage line.
Compared to an exclusively non-overlapped switching, it is an advantage of the invention that it reduces the current kickback and the voltage overshoot present with inductive loads. Thereby, also the ESD and substrate noise is reduced.
Moreover, the requirements for the ESD area are relieved, as the power switches of the switching stages with overlapped clocking have an additional role of acting as protection devices, while at the same time current spikes are avoided. The power switches of the output stage according to the invention further have an additional function of smoothing transients and overshoot voltages, thus less or no additional components are needed for protecting the ESD structures.
The total area required for the output stage does not have to be increased either for realizing the invention. For a desired drive capability, it is sufficient to segment the existing area into smaller areas, each comprising one of the switching stages.
An advantage is already reached with a segmentation of the output stage to only one switching stage for which overlapped switching is employed and one switching stage for which non-overlapped switching is employed. But the segmentation can also be extended further to more than 2 parallel switching stages. It might be convenient to select a segmentation of 2N parallel switching stages, where N is a natural number.
In a preferred embodiment of the invention, at least three switching stages are provided and a larger portion of the provided switching stages is switched in an non-overlapped fashion, while a smaller portion of the provided switching stages is switched in an overlapped fashion.
In a further preferred embodiment of the invention, most of the total drive capability is distributed to the switching stages for which a non-overlapped switching is employed, while the rest is distributed to the switching stages for which an overlapped switching is employed. Preferably, about 90% of the total drive capability is distributed to the switching stages for which a non-overlapped switching is employed. As a result, the power provided by the non-overlapping switching stages is higher than the power provided by the overlapping switching stages. Additionally, the physical size of the different switching stages may be different. Alternatively, the size and the drive capability of the different switching stages and the power provided by the different switching stages may be equal.
In another preferred embodiment of the invention, the different non-overlapping switching stages are switched successively with a delay in switching between each switching stage, such that the effective slope of the rising and falling edges at the output of the complete segmented output stage are less abrupt. This attenuates high frequencies of the EMC noise, frequencies above 10 MHz, which is desirable in devices containing RF receivers. The phased clocking required for enabling a switching of the different switching stages with delays in between can be realized in any suitable manner.
In addition to a phased clocking, the segmented switching stages can be dimensioned by dividing the area into segments of unequal sizes. This enables a better control of the high frequency contents of the output of the output stage. For example, the dimensioning can be made such that the edges of the output of the output stage are effectively filtered with a Gaussian filter or with another filter of known properties.
The number and dimensions of the switching stages and the exact sizing of the power switches employed in the switching stages can be selected in any suitable manner.
Further, the employed switching stages can be single-ended output stages as well as differential output stages.
The invention can be implemented with discrete components, but it is most advantageous when the output stage is integrated in a semiconductor circuit. In the latter case, the clocking means could be integrated in addition in the same semiconductor circuit.
The invention is moreover applicable to any switching power amplifiers, in particular to audio switching power amplifiers and RF switching power amplifiers.